This application claims the benefit of EPO application serial No. 99250060.3 filed Mar. 3, 1999, which is hereby incorporated herein by reference, and which claims the benefit under 35 U.S.C. xc2xa7365 of International Application PCT/EP00/01413, filed Feb. 21, 2000, which was published in accordance with PCT Article 21(2) on Sep. 8, 2000 in English.
The present invention relates to a method and to an apparatus for transferring data on a bus to or from a device to be controlled by said bus, wherein bus blocking is to be avoided.
The IEEE1394 bus is a low cost, high performance serial bus. It has a read/write memory architecture and a highly sophisticated communication protocol. Data rates of 100, 200 or 400 Mbit/s can be transmitted in nearly real time. Simultaneously, data can be transmitted bi-directionally. The first ten bits of transmitted address values refer to one of up to 1023 possible IEEE1394 bus clusters. The following six bits of the transmitted address values refer within a specific cluster to one of up to 63 nodes to which an application or device is assigned. Data between nodes can be exchanged without interaction of a host controller. Devices can be connected to or disrupted from the network at any time, allowing a plug and play behaviour.
The standardised cable connection for the nodes has a length of 4.5 m and contains three twisted cable pairs of which two pairs serve for data and control information transmission and the further pair carries supply voltages of 8V to 40V. Three level coding is used: HIGH (H), LOW (L), and HIGH IMPEDANCE (Z). H overrides L, L overrides Z. The characteristic impedance is 110 xcexa9. There is also a version IEEE1394-1995 of the bus specification including only two twisted pairs of cables on which no power supply voltage is present. The communication protocol has three layers: physical layer, link layer, and transaction layer. Typically, the transaction layer is realised by firmware whereas the other layers are implemented using chip sets.
The physical layer contains analog transceivers and a digital state machine. It handles bus auto-configuration and hot plug. It reclocks, regenerates and repeats all packets and forwards all packets to the local link layer. It carries out-packet framing, for example speed code, prefix, and packet end assembling. It arbitrates and transmits packets from the local link layer. Available IC types are e.g. TSB11C01, TSB11LV01, TSB21LV03, and TSB41LV03 of Texas Instruments, MB86611 of Fujitsu, and 21S750 of IBM.
The link layer performs all digital logic. It recognises packets addressed to the node by address recognition and decodes the packet headers. It delivers packets to higher layers and generates packets from higher layers. It works either isochronous for AV data use or asynchronous for control data use.
In the isochronous mode a channel having a guaranteed bandwidth is established. There is a defined latency. The transmission is performed in 125 xcexcs time slots or cycles. Headers and data blocks of a packet have separate CRCs (cyclic redundancy check). This mode has a higher priority than the asynchronous data transfer mode.
The asynchronous mode is not time critical, but safe. It operates as an acknowledged service with a busy and retry protocol. Fixed addresses are used. Transmission takes place when the bus is idle. The asynchronous mode handles read request/response, write request/response, and lock request/ response. It performs cycle control, CRC generation and validation. Available link layer IC types are e.g. TSB12C01A, TSB12LV21, TSB12LV31, and TSB12LV41 of Texas Instruments, and PDI1394L11 of Philips.
The transaction layer implements asynchronous bus transactions:
Read request/read response
Write request/write response
Lock request/lock response
As mentioned above it can be implemented by software running on a microcontroller, such as e.g. the 1960 of SparcLite. There may also be an AV (audio video) layer carrying out device control, connection management, timestamping, and packetising.
A link layer IC implements the interface to an external application, e.g. a VCR, and prepares IEEE1394 data for sending on the IEEE1394 bus, or interprets incoming IEEE1394 data packets from the IEEE1394 bus. A physical layer IC implements the direct electrical connection to the bus and controls many functions as mentioned above, including arbitration for sending data on the bus. The procedure for sending data from a link layer IC onto the bus is that the link layer IC requests access to the bus and then waits until the physical layer IC grants the desired access. Upon detecting the grant status, the link layer IC is free to send data onto the bus. But if in the meantime the link layer status has changed, i.e. the link layer IC refrains from sending data onto the bus, the granted bus access will not be given up according to the current IEEE1394 bus specification. As a consequence the bus is blocked for an indefinite time period because the bus access granted cannot be overwritten by the physical layer IC. A bus lock-up is very serious and means that the whole bus is jammed, no other node can get access to the bus to send data.
According to the invention an additional timer function is implemented in the link layer IC. This xe2x80x98bus grant missedxe2x80x99 timer function controls the link layer IC in such a way that it automatically gives back the bus control to the physical layer IC after a predetermined fixed time period has elapsed during which the link layer IC has sent no data onto the bus. The predetermined fixed time period can be user programmable in order to adapt it to a given bus configuration or application, respectively.
It is one object of the invention to disclose a method for avoiding bus blocking in case a granted bus access in not used for sending data onto the bus. This object is achieved by the method disclosed in claim 1.
It is a further object of the invention to disclose an apparatus which utilises the inventive method. This object is achieved by the apparatuses disclosed in claim 3.
In principle, the inventive method is suited for transferring data on a bus to or from a device to be controlled by said bus, wherein for interfacing between the bus and said device a physical layer IC and a link layer IC are used and wherein said physical layer IC generates a grant signal in order to give to said link layer IC access to said bus for sending data onto said bus and until said link layer IC has finished sending said data onto said bus following said grant signal, said bus remains occupied by said link layer IC, wherein said link layer IC includes a timer function which in case said physical layer IC grants to said link layer IC access for sending data onto said bus but said link layer IC does not send data onto said bus, generates a link release signal in order to release the link layer IC bus occupation after a predetermined time period following said grant signal has elapsed.
Advantageous additional embodiments of the inventive method are disclosed in the respective dependent claim.
In principle the inventive bus interface is suited for transferring data to or from a device to be controlled by the bus, and includes:
a link layer IC for connection to said device;
a physical layer IC for connection to said bus, wherein said physical layer IC generates a grant signal in order to give to said link layer IC access to said bus for sending data onto said bus and wherein, until said link layer IC has finished sending said data onto said bus following said grant signal, said link layer IC keeps said bus occupied;
a timer included in said link layer IC which in case said physical layer IC grants to said link layer IC access for sending data onto said bus but said link layer IC does not send data onto said bus, generates a link release signal in order to release the link layer IC bus occupation after a predetermined time period following said grant signal has elapsed.

Advantageous additional embodiments of the inventive apparatus are disclosed in the respective dependent claim.